SPIxCON1

SPIxCON1

SPI Control Register 1
  0x01DC 8   1 1 x

SPIxCON1

Bit  7 6 5 4 3 2 1 0  
  SMP CKE CKP FST   SSP SDIP SDOP  
Access  R/W R/W R/W R/W   R/W R/W R/W  
Reset  0 0 0 0   1 0 0  

Bit 7 – SMP: SPI Input Sample Phase Control

SPI Input Sample Phase Control

ValueNameDescription
1 Client Reserved
1 Host SDI input is sampled at the end of data output time
0 Client or Host SDI input is sampled in the middle of data output time

Bit 6 – CKE: Clock Edge Select

Clock Edge Select

ValueDescription
1 Output data changes on transition from Active to Idle clock state
0 Output data changes on transition from Idle to Active clock state

Bit 5 – CKP: Clock Polarity Select

Clock Polarity Select

ValueDescription
1 Idle state for SCK is high level
0 Idle state for SCK is low level

Bit 4 – FST: Fast Start Enable

Fast Start Enable

ValueNameDescription
x Client This bit is ignored
1 Host Delay to first SCK may be less than ½ baud period
0 Host Delay to first SCK will be at least ½ baud period

Bit 2 – SSP: Client Select Input/Output Polarity Control

Client Select Input/Output Polarity Control

ValueDescription
1 SS is active-low
0 SS is active-high

Bit 1 – SDIP: SPI Input Polarity Control

SPI Input Polarity Control

ValueDescription
1 SDI input is active-low
0 SDI input is active-high

Bit 0 – SDOP: SPI Output Polarity Control

SPI Output Polarity Control

ValueDescription
1 SDO output is active-low
0 SDO output is active-high