While a data transfer is in progress, the SPI hardware sets the
BUSY bit. This bit can be polled by the user to determine the current
status of the SPI module, and to know when a communication is complete. The following
registers and bits will not be changed by software while the BUSY bit is set:
- SPIxTCNT
- SPIxTWIDTH
- SPIxCON2
- The CLB bit
Important:
- 1.The BUSY bit is subject to
synchronization delay of up to two instruction cycles. The user must wait for it
to set after loading the transmit buffer (SPIxTXB register) before using it to
determine the status of the SPI module.
- 2.It is also not recommended to
read SPIxTCNT while the BUSY bit is set, as the value in the registers may not
be a reliable indicator of the transfer counter. Use the TCZIF bit to accurately determine that the transfer
counter has reached zero.