In Multi-Host mode, multiple host devices reside on the same bus. A single device, or all
devices, may act as both a host and a client. Control of the bus is achieved through
clock synchronization and bus arbitration.
The Bus Free (
BFRE) bit is used to determine if the bus is free. When BFRE is
set (BFRE =
1), the bus is in an Idle state, allowing a host device to
take control of the bus.
In Multi-Host mode, the Address Interrupt and Hold Enable (
ADRIE) bit must be set (ADRIE =
1), and the Clock
Stretching Disable (
CSD) bit must be clear (CSD =
0), in order for a host
device to be addressed as a client.
When a matching address is received into the receive shift register, the
SMA bit is set, and the Address Interrupt Flag (
ADRIF) bit is set. Since
ADRIE is also set, hardware sets the Client Clock Stretching (
CSTR) bit, and hardware stretches the clock to allow time for software to
respond to the host device being addressed as a client. Once the address has been
processed, software must clear CSTR to resume communication.
Important: Client hardware has
priority over host hardware in Multi-Host mode. Host mode communication can only be
initiated when
SMA =
0.