I2C Backward Compatibility

The I3C SDR mode is backward compatible with I2C protocol and conditions, which allows for legacy I2C target devices (but not I2C Controller devices) to coexist with I3C devices on the same I3C bus. Since the I3C protocol is designed to allow I2C traffic on the bus, the I3C targets can easily ignore the I2C traffic. However, most legacy I2C targets on the bus will not see the I3C traffic because of the higher I3C clock speeds. Refer to 2I3C Pad Compatibility with IC/SMBus Levels for details.

Important: The MIPI I3C® Specification strongly suggests that legacy I2C devices incorporate 50 ns spike filters on the SDA and SCL pads to make it possible for them to ignore the I3C traffic at higher speeds. With spike filters implemented for all I2C targets on the bus, the I3C bus can operate at the maximum rated clock frequency. If any I2C target on the bus does not have spike filters implemented or activated, then the I3C bus speed is determined by the slowest I2C target without a spike filter.
Tip: The I3C Target module on this device can be used in I2C Target mode until it is assigned a Dynamic Address. Refer to 2Legacy IC Transaction on I3C Bus for details. If I2C Controller features are desired, refer to the “I2C - Inter-Integrated Circuit Module” chapter for more information.

Table 1 outlines some similarities and variations that exist between the I3C SDR protocol and the I2C standard protocol.

Table 1. I2C Standard vs I3C® SDR Protocol Differences
Feature I2C Feature Supported in I3C Protocol Feature as Implemented in I3C Protocol
Bus Speed

Fast mode (400 kHz) required

Fast mode Plus (1 MHz) desired
Up to 12.5 MHz
Operating Voltage 1.8V to 3.6V 1V to 3.6V

7-bit Static Address supported

10-bit Extended Static Address not supported

7-bit Static Address

7-bit Dynamic Address
50 ns Spike Filters Highly recommended N/A
Clock Stretching by Target Not supported Feature does not exist in I3C since SCL line is only driven by the Controller
I3C® Reserved Address (7’h7E) Not allowed Used to begin an I3C SDR transaction on the bus
Start, Restart, and Stop Conditions Supported Identical to I2C
Address Header Supported Identical to I2C in bit formatting, although signaling and timing may vary
Data Word Supported Same bit count as I2C, but differ in the ninth bit
Signaling Always open-drain, supported Normally push-pull, some exceptions may use open-drain. Pull-ups are provided by the Controller.