Transmit and Receive Buffers

This Target module contains separate independent Transmit and Receive Buffers which the user software can interact with to send data to and receive data from the Target. The user can write to I3CxTXB Transmit Buffer Register to send data onto the bus. The I3CxRXB Receive Buffer Register contains data the Target receives from the Controller that the user can read. The Transmit and Receive Buffers are each equipped with separate dedicated FIFOs. Both the Transmit and Receive FIFOs on this Target module are 16 bytes each. The user can only send and receive data through the I3CxTXB Transmit and I3CxRXB Receive Buffers, the Transmit and Receive FIFOs are not user accessible. The CLRTXB and CLRRXB bits in the I3CxCON register can be used to clear the Transmit and Receive Buffers and FIFOs.

The I3CxTXB Transmit Buffer is safe to write when it is empty. This condition is represented through the Transmit Buffer Empty TXBE bit. This also results in the I3CxTXIF system level interrupt flag being set, which can also be used as a DMA trigger.

When data is written to I3CxTXB register, the TXBE and I3CxTXIF bits are cleared indicating that the Transmit Buffer is full. When possible, this data is immediately passed onto the Transmit FIFO and the TXBE and I3CxTXIF bits are set again indicating that the Transmit Buffer is empty and ready to be written. If the data is written to the I3CxTXB Transmit Buffer faster than the Controller’s reading speed, it is possible that the Transmit FIFO will become full and the TXBE and I3CxTXIF bits will remain cleared until data is transmitted onto the bus. If the I3CxTXB Transmit Buffer is written to when it is full (TXBE = 0), a Transmit Buffer Write Error occurs and TXWEIF interrupt flag is set. Alternatively, it is also possible that the Controller attempts to read from the Target when the Transmit FIFO is empty, in which case a Transmit Underrun occurs, TXUIF interrupt flag is set and the read request is NACKed by the Target (if operating in I²C mode).

The I3CxRXB Receive Buffer is safe to read when it is full. This condition is represented through the Receive Buffer Full RXBF bit. This also sets the I3CxRXIF system level interrupt flag, which can also be used as a DMA trigger.

When the Target receives data from the Controller on the bus, it is received in the Receive FIFO. This data is immediately passed onto the I3CxRXB register, thus setting the RXBF and I3CxRXIF bits indicating that the Receive Buffer is full. Once this data is read by the user software, the RXBF and I3CxRXIF bits are cleared indicating that the Receive Buffer is empty. If there is data waiting in the Receive FIFO, it is immediately transferred to the I3CxRXB register, thus setting the RXBF and I3CxRXIF bits again. If the I3CxRXB Receive Buffer is read when it is empty (RXBF = 0), then a Receive Buffer Read Error occurs and the RXREIF interrupt flag is set. If the data is being read from the I3CxRXB Receive Buffer slower than the Controller’s writing speed, it is possible that the Receive FIFO will become full. If the Controller continues to write data to a full Receive FIFO, a Receive Overrun occurs, RXOIF interrupt flag is set and the write request is NACKed by the Target (if operating in I²C mode).