CLCnGLS3

CLCnGLS3

CLCn Gate4 Logic Select Register
  0x1AE 8  

CLCnGLS3

Bit  7 6 5 4 3 2 1 0  
  G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  x x x x x x x x  

Bits 1, 3, 5, 7 – G4DyT: dyT: Gate4 Data ‘y’ True (noninverted)

dyT: Gate4 Data ‘y’ True (noninverted)

ValueDescription
1 dyT is gated into g4
0 dyT is not gated into g4

Bits 0, 2, 4, 6 – G4DyN: dyN: Gate4 Data ‘y’ Negated (inverted)

dyN: Gate4 Data ‘y’ Negated (inverted)

ValueDescription
1 dyN is gated into g4
0 dyN is not gated into g4