CLKRCON

CLKRCON

Reference Clock Control Register
Note:
  1. 1.Bits are valid for DIV ≥ 001. For DIV = 000, duty cycle is fixed at 50%.
  0x100 8  

CLKRCON

Bit  7 6 5 4 3 2 1 0  
  EN     DC[1:0] DIV[2:0]  
Access  R/W     R/W R/W R/W R/W R/W  
Reset  0     1 0 0 0 0  

Bit 7 – EN: Reference Clock Module Enable

Reference Clock Module Enable

ValueDescription
1 Reference clock module enabled
0 Reference clock module is disabled

Bits 4:3 – DC[1:0]: Reference Clock Duty Cycle(1)

Reference Clock Duty Cycle(1)

ValueDescription
11 Clock outputs duty cycle of 75%
10 Clock outputs duty cycle of 50%
01 Clock outputs duty cycle of 25%
00 Clock outputs duty cycle of 0%

Bits 2:0 – DIV[2:0]: Reference Clock Divider

Reference Clock Divider

ValueDescription
111 Base clock value divided by 128
110 Base clock value divided by 64
101 Base clock value divided by 32
100 Base clock value divided by 16
011 Base clock value divided by 8
010 Base clock value divided by 4
001 Base clock value divided by 2
000 Base clock value