Dynamic Address Assignment

The Main Controller performs the Dynamic Address Assignment procedure to provide a unique Dynamic Address to each device connected to the I3C bus. The Main Controller provides a Dynamic Address to the Target upon initialization of the I3C bus, or when a Target is newly connected to an already configured I3C bus and performs a Hot-Join request. Once the Dynamic Address has been assigned, it is stored in the I3CxDADR Dynamic Address register, and the Target starts to operate in I3C SDR mode (OPMD = 0b01).

Until a Dynamic Address is assigned, the Target operates in I2C mode (OPMD = 0b00) and uses a 7-bit I2C static address, which is stored in the I3CxSADR Static Address register, to represent itself on the bus. The Target is backward-compatible to I2C in this mode and can respond to both I2C and SMBus traffic on the bus.

Important: Dynamic Address Assignment only switches the Target’s mode of operation from I2C mode to I3C SDR mode, but it does not change the buffers on SDA and SCL pads. If the user has enabled the glitch filter and I2C/SMBus buffers on the pads through the I3CxI2CCON and RxyI2C registers, the user will have to manually disable them to switch back to I3C buffers on the pads. Refer to 2I3C Pad Compatibility with IC/SMBus Levels for details. The user can check the OPMD bits when the Dynamic Address Assignment procedure is complete (or cleared) and switch the buffers accordingly.