PORTWDF

PORTWDF

Virtual Port Data Flop Control
Note:
  1. 1.This register can only be written when the clock to the module is disabled. See Virtual Port Clock section for details.
  0x04A4 8   1 W W

PORTWDF

Bit  7 6 5 4 3 2 1 0  
  DF7 DF6 DF5 DF4 DF3 DF2 DF1 DF0  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 0, 1, 2, 3, 4, 5, 6, 7 – DFn: Virtual Port Data Flop Enable

Virtual Port Data Flop Enable

ValueDescription
1 Virtual Port input routed through flip-flop to output
0 Virtual Port input connected directly to output