Standard GPIO Buffers as I3C Pads

The I3C SDA and SCL pads are equipped with fast Schmitt Triggers as Standard GPIO Buffers that comply with the I3C bus specification for VDDIOx pin voltages above 1.62V. Although the I3C Low-Voltage Buffers are effective throughout the full I3C operating voltage range of 1V-3.63V, it is recommended to use Standard GPIO Schmitt Trigger Buffers for I3C voltages greater than 1.62V to save power. Since the Schmitt Trigger Buffers are not effective below 1.62V, the I3C Low-Voltage Buffers are auto-enabled when the voltage on the corresponding VDDIOx pin drops below 1.62V if the bandgap reference is already enabled (see Caution below). The I3C Low-Voltage Buffers are auto-disabled when the VDDIOx pin voltage climbs back above 1.62V unless the corresponding VDDIOxLVEN bit in the IOLVCON register is set.

To use these buffers, the Threshold TH bits in the corresponding RxyI2C register must select Standard GPIO Buffers, and the I3C Low-Voltage Buffers on that voltage domain need to be disabled through the VDDIOxLVEN bit in the IOLVCON register. As the I3C module is enabled (EN = 1), the Schmitt Trigger Buffers will be selected regardless of the INLVLx register settings.
Tip: It is recommended to disable any slew rate control and pull-ups using SLEW and PU bits in the corresponding RxyI2C register to remain compliant with the MIPI I3C® Specification.
CAUTION: The I3C Low-Voltage Buffers require the bandgap reference voltage to become active once auto-enabled. However, when the VDDIOx power drops below 1.62V, the corresponding domain is held in power-on reset state and bandgap reference cannot be requested. Hence, it is highly recommended for the users to manually request for bandgap reference voltage (by enabling the FVR module) should they expect VDDIOx to lose power and drop below 1.62V so that the I3C Low-Voltage Buffers are auto-enabled and activated immediately.