Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and PCON0 registers are updated to indicate the cause of the Reset. The following table shows the Reset conditions of these registers.

Table 1. Reset Condition for Special Registers
Condition Program
Counter STATUS Register(1,2) PCON0 Register PCON1 Register
Power-on Reset 0 -110 0000 0011 110x ---- -111
Brown-out Reset 0 -110 0000 0011 11u0 ---- -u1u
MCLR Reset during normal operation 0 -uuu uuuu uuuu 0uuu ---- -uuu
MCLR Reset during Sleep 0 -10u uuuu uuuu 0uuu ---- -uuu
WDT Time-out Reset 0 -0uu uuuu uuu0 uuuu ---- -uuu
WDT Wake-up from Sleep PC + 2 -00u uuuu uuuu uuuu ---- -uuu
WWDT Window Violation Reset 0 -uuu uuuu uu0u uuuu ---- -uuu
Interrupt Wake-up from Sleep PC + 2(3) -10u uuuu uuuu uuuu ---- -uuu
RESET Instruction Executed 0 -uuu uuuu uuuu u0uu ---- -uuu
Stack Overflow Reset (STVREN = 1) 0 -uuu uuuu 1uuu uuuu ---- -uuu
Stack Underflow Reset (STVREN = 1) 0 -uuu uuuu u1uu uuuu ---- -uuu
Data Protection (Fuse Fault) 0 -uuu uuuu uuuu uuuu ---- -uu0
VREG or ULP Ready Fault 0 -110 0000 0011 110u ---- -0u1
Memory Violation Reset 0 -uuu uuuu uuuu uuuu ---- -u0u

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Notes:
  1. 1.If a Status bit is not implemented, that bit will be read as ‘0’.
  2. 2.Status bits Z, C, DC are reset by POR/BOR.
  3. 3.When the wake-up is due to an interrupt and Global Interrupt Enable (GIE) bit is set, the return address is pushed on the stack and PC is loaded with the corresponding interrupt vector (depending on source, high or low priority) after execution of PC + 2.