I3CxBAVL

I3CxBAVL

Bus Available Condition Threshold

Note: The value of this register is determined as the number of I3CxCLK clocks corresponding to a 1 μs Bus Available Condition. An internal counter incremented by the I3CxCLK clock is compared against this value to determine when a Bus Available Condition occurs. Refer to section Bus Available Condition for details.
0x092, 0x0C3 8     1index x

I3CxBAVL

Bit  7 6 5 4 3 2 1 0  
  BAVL[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:0 – BAVL[7:0]: Bus Available Condition Threshold

Bus Available Condition Threshold