Receiver Parity Modes

Even or odd parity is automatically detected when the MODE bits are set to ‘0011’ or ‘0010’, respectively. The parity modes receive eight data bits and one parity bit for a total of nine bits for each character. The PERIF bit represents the parity error of the top unread character of the receive FIFO rather than the parity bit itself. The parity error must be read before the UxRXB register is read because reading the UxRXB register will advance the FIFO pointer to the next byte with its associated PERIF flag.

A parity error will generate a summary UxEIF interrupt when the PERIE bit is set. The summary error is reset when the PERIF bit of the top of the FIFO is ‘0’ or when all FIFO characters have been retrieved.

Important: When PERIE is set, the UxRXIF interrupts are suppressed by PERIF = 1.