I3C Dynamic Address

In addition to the Static Address described above, every I3C device on the bus also has a 7-bit Dynamic Address which is assigned by the Controller through the Dynamic Address Assignment process or the Hot-Join Mechanism. This Target module stores the Dynamic Address in the I3CxDADR register. Once the Target receives its Dynamic Address from the Controller, it starts to operate in I3C SDR mode (OPMD = 0b01) and will no longer respond to the Static Address. The Controller communicates with the Target at I3C speeds once it is assigned a Dynamic Address.

While the Target is operating in I3C SDR mode, the Controller can engage with the Target in the following ways:

  • Private Read/Write Transaction
  • Broadcast Common Command Code (CCC) Write Transaction
  • Direct CCC Read/Write Transaction
  • In-Band Interrupt (IBI) Transaction
The Target sets the DADRIF interrupt flag when it detects the Controller has transmitted the Target’s Dynamic Address on the bus during a Direct CCC or a Private Transaction.

The Target’s Dynamic Address transmitted on the bus immediately following a Start (but not a Restart condition) is subject to arbitration, meaning both the Controller and the Target can drive the Target’s Dynamic Address after a Start condition.

  • The Controller can transmit the Target’s Dynamic Address following a Start condition to initiate a Private Transaction. The Controller also transmits a R/W bit along with the Dynamic Address. When R/W= 1 (read), the Controller initiates a Private Read Transaction, whereas R/W = 0 (write) signifies a Private Write Transaction. The Target responds to this request by acknowledging (or not acknowledging) through the ACK/NACK bit that follows the R/W bit.
  • The Target can transmit its own Dynamic Address following a Start condition to initiate an IBI request. An IBI request is always made in Read mode (the Target releases SDA high for R/W bit). The Controller responds to this request by acknowledging (or not acknowledging) through the ACK/NACK bit that follows the R/W bit. Refer to section In-Band Interrupt (IBI) for details on Controller actions during an IBI transaction.

Since the address header following a Start condition is arbitrable, both the cases mentioned above can happen concurrently. The I3C protocol has systems in place for proper resolution of such a situation.

  • The Target must wait for at-least a Bus Available Condition to initiate an IBI request, which is much longer than the Bus Free Condition that the Controller has to wait before transmitting a Start following a Stop condition. This difference in timing allows the Controller to communicate with the Target first (before the Target has the chance to initiate communication with the Controller).
  • An IBI request is always made by the Target transmitting its Dynamic Address in Read mode (R/W bit = 1).
    • If the Controller is transmitting the Target’s Dynamic Address at the same time in Write mode (R/W bit = 0) to initiate a Private Write Transaction, then the Target loses arbitration and must receive the data the Controller is sending. Refer to section I3C Address Arbitration for more information on how address arbitration takes place. Refer to section Private Transaction on how a Private Write Transaction takes place.
    • If the Controller is transmitting the Target’s Dynamic Address at the same time in Read mode (R/W bit = 1) to initiate a Private Read Transaction, then both the Controller and the Target end up sending the same data on the bus. In this case, since both the Controller and Target are expecting an ACK from each other, but neither pulls the SDA low for an ACK, a passive NACK is implied on the bus and the Controller ends the transaction.