I3C Address Header

The I3C Address Header follows either a Start or a Restart condition and follows the same format as an I2C Address Header – 7 Address bits, one R/W bit, and one ACK/NACK bit.

The Address Header following a Start Condition (but not a Restart condition) is subject to arbitration. This means that multiple devices may be attempting to drive an address on the bus using the SDA lines, and therefore is transmitted in Open-Drain mode. Refer to I3C Address Arbitration for more information.

Figure 1. Open-Drain Generic Address Header Timing Diagram

The Address Header following a Restart condition is not subject to any arbitration, meaning only the Controller drives an address on the bus, and therefore is always transmitted in Push-Pull mode. Figure 2 shows a non-arbitrable Address Header in Push-Pull mode.

Figure 2. Non-Arbitrable Address Header in Push-Pull Mode
The device (Controller or Target) transmitting the 7-bit address in the address header also transmits the R/W bit in the address header. The device transmits a low signal on SDA line (R/W bit = 0) to represent Write mode (the Controller writing to the Target). The device transmits a high signal on SDA line (R/W bit = 1) to represent Read mode (the Controller reading from the Target). The R/W bit follows the same signaling (Open-Drain or Push-Pull) as that of the 7 Address bits preceding it. In a Private I3C/I2C Transaction, the status of the R/W bit is captured in the RNW bits.

Once the device transmits the first eight bits of the address header on the bus, it waits for the other device (the Controller waits for the Target, the Target waits for the Controller) to acknowledge (or not acknowledge) the request. This is done through the ninth ACK/NACK bit in the address header. The ACK/NACK bit is always transmitted in Open-Drain regardless of the signaling used to transmit the first eight bits. The responding device pulls the SDA line low (ACK/NACK bit = 0) to respond with an acknowledge (ACK), whereas the responding device releases the SDA line high (ACK/NACK bit = 1) to respond with a non-acknowledge (NACK). This Target module typically ACKs any request from the Controller unless one of the buffer error conditions occurs as mentioned in Transmit and Receive Buffers, in which case the Target NACKs the request.

Important: Once the Target sends a NACK on the bus, the Target will NACK all subsequent communication on the bus until the error conditions are cleared.

The following address types can be transmitted on the I3C bus: