# Data Gating

Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs.

The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or noninverted data. Directed signals are ANDed together in each gate. The output of each gate can be inverted before going on to the logic function stage.

The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the output is inverted, the gate is an AND of all enabled data inputs. When the inputs and output are not inverted, the gate is an OR or all enabled inputs.

Table 1 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be ‘0’ or ‘1’, depending on the gate output polarity bit.

Table 1. Data Gating Logic
CLCnGLSy GyPOL Gate Logic
0x55 1 AND
0x55 0 NAND
0xAA 1 NOR
0xAA 0 OR
0x00 0 Logic ‘0
0x00 1 Logic ‘1

It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is ‘0’, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output of the channel must be ‘0’ or ‘1’, the recommended method is to set all gate bits to ‘0’ and use the gate polarity bit to set the desired level.

Data gating is configured with the logic gate select registers as follows:
Note: Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register.

Data gating is indicated in the right side of Figure 1. Only one gate is shown in detail. The remaining three gates are configured identically, except when the data enables correspond to the enables for that gate.