TxCLK

TxCLK

Timer Clock Source Selection Register
  0x010C 8   1 1 x

TxCLK

Bit  7 6 5 4 3 2 1 0  
          CS[3:0]  
Access          R/W R/W R/W R/W  
Reset          0 0 0 0  

Bits 3:0 – CS[3:0]: Timer Clock Source Selection

Timer Clock Source Selection

Table 1. Timer Clock Sources
CS Clock Source
Timer1
1111 CLC4_OUT
1110 CLC3_OUT
1101 CLC2_OUT
1100 CLC1_OUT
1011 TMR0_OUT
1010 CLKREF_OUT
1001 EXTOSC
1000 SOSC
0111 MFINTOSC (32 kHz)
0110 MFINTOSC (500 kHz)
0101 SFINTOSC
0100 LFINTOSC
0011 HFINTOSC
0010 FOSC
0001 FOSC/4
0000 Pin selected by T1CKIPPS