TxHLT

TxHLT

Timer Hardware Limit Control Register
Notes:
  1. 1.Setting this bit ensures that reading TxTMR will return a valid data value.
  2. 2.When this bit is ‘1’, the Timer cannot operate in Sleep mode.
  3. 3.CKPOL must not be changed while ON = 1.
  4. 4.Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
  5. 5.When this bit is set, then the timer operation will be delayed by two input clocks after the ON bit is set.
  6. 6.Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value of TxTMR).
  7. 7.When TxTMR = TxPR, the next clock clears TxTMR, regardless of the operating mode.
  0x11C,0x122 8   2,4 x

TxHLT

Bit  7 6 5 4 3 2 1 0  
  PSYNC CPOL CSYNC MODE[4:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bit 7 – PSYNC: Timer Prescaler Synchronization Enable(1, 2)

Timer Prescaler Synchronization Enable(1, 2)

ValueDescription
1 Timer Prescaler Output is synchronized to FOSC/4
0 Timer Prescaler Output is not synchronized to FOSC/4

Bit 6 – CPOL: Timer Clock Polarity Selection(3)

Timer Clock Polarity Selection(3)

ValueDescription
1 Falling edge of input clock clocks timer/prescaler
0 Rising edge of input clock clocks timer/prescaler

Bit 5 – CSYNC: Timer Clock Synchronization Enable(4, 5)

Timer Clock Synchronization Enable(4, 5)

ValueDescription
1 ON bit is synchronized to timer clock input
0 ON bit is not synchronized to timer clock input

Bits 4:0 – MODE[4:0]: Timer Control Mode Selection(6, 7)

Timer Control Mode Selection(6, 7)

ValueDescription
00000 to 11111 See Table 1