CLCnGLS1

CLCnGLS1

CLCn Gate2 Logic Select Register
  0x1AC 8  

CLCnGLS1

Bit  7 6 5 4 3 2 1 0  
  G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  x x x x x x x x  

Bits 1, 3, 5, 7 – G2DyT: dyT: Gate2 Data ‘y’ True (noninverted)

dyT: Gate2 Data ‘y’ True (noninverted)

ValueDescription
1 dyT is gated into g2
0 dyT is not gated into g2

Bits 0, 2, 4, 6 – G2DyN: dyN: Gate2 Data ‘y’ Negated (inverted)

dyN: Gate2 Data ‘y’ Negated (inverted)

ValueDescription
1 dyN is gated into g2
0 dyN is not gated into g2