Error Type TE0

Error Type TE0 occurs when the Target receives an invalid Broadcast Address 7’h7E/W or Dynamic Address/R/W from the Controller after being assigned a Dynamic Address. When this happens, the Target is unable to distinguish whether the transfer is a CCC transfer or a Private R/W transfer. Since it cannot distinguish the CCC transfer, the Target would be unaware if the Controller enters HDR mode and might attempt to interpret HDR transfer as though the bus were still in SDR mode, which could become potentially fatal when not handled properly.

The Target detects this error by monitoring the bus for any of the following invalid combinations of Broadcast Address/W: 7’h3E / W, 7’h5E / W, 7’h6E / W, 7’h76 / W, 7’h7A / W, 7’h7C / W, 7’h7F / W, or 7’h7E / R. The Target can also detect this error when its own Dynamic Address is invalid on the bus, however the probability of such a detection is extremely low. The TE0ERR bit and the BUSEIF Bus Error Interrupt Flag are set upon successful detection of TE0 type error. Once set, the TE0ERR and BUSEIF bits will not self-clear. The user must clear them in software to re-arm the functionality of each bit individually.

The Target recovers from this Error condition by enabling the HDR Exit Detector and ignoring the rest of the patterns on the bus. The Target also monitors SDA and SCL lines to detect SDR mode. If both the SDA and SCL lines stay High for at least 60 µs(1), then the Target accepts that the bus is operating in non-HDR mode, and it will wait for the next Stop or Restart to resume normal operation.

  1. 1.The 60 µs wait time is derived from the slowest HDR speed. The slowest HDR clock is 10 kHz with a total cycle time of 100 µs. It is assumed that an HDR mode will keep an approximately even duty cycle at slow clock speeds, thus making 60% of the duty cycle (or 60 µs) a safe wait time.