The stop event for the counter/timer stop is selected using the
STOP bits in the TUxyHLT register. The available options
include:
- 1.No hardware Stop: The counter/timer
runs continuously until the ON bit is cleared. Neither the ERS signal nor a PR register
match will stop the counter/timer. This is the software-controlled stop option. The
current counter value is captured in the TUxyCR capture register at every rising
edge of ERS signal, in which case the TUxyCR capture register must be read before
the event of a second ERS rising or the captured data will be overwritten by the
second rising event. When the EPOL bit is set, the polarity is inverted and the counter
value is captured at every falling edge of ERS signal instead.
- 2.Either edge of the ERS signal
(edge-triggered): The counter/timer stops at the event of either the rising or
falling edge of the ERS signal and the counter value is captured in the TUxyCR
capture register. See Figure 3 for an example of rising ERS edge Start and either ERS edge Stop
condition.
- 3.Rising edge of the ERS signal
(edge-triggered): The counter/timer stops at the event of a rising edge of the ERS
signal and the counter value is captured in the TUxyCR capture register. When the
EPOL bit is set, the polarity is inverted and the counter/timer stops at the falling
edge of the ERS signal.
- 4.At period match: The counter/timer
stops when the TUxyTMR counter register is equal to the TUxyPR period register and
the counter value is captured in the TUxyCR capture register. See Figure 4 for an example of Stop at PR match.
Important:
- 1.In the event of coincidental start and stop events, and RUN =
0; the start event takes precedence, timer capture and
CIF interrupt are blocked, and OSEN is ignored. See Figure 1 for a coincidental start and stop event at
ERS rising edge. If RUN = 1, then the stop event is
ignored, but will still cause a capture.
- 2.If Reset and Stop are coincident, the captured value is the value prior to
the Reset and the counter will stop at zero.
- 3.After stopping, the start
edge detector needs up to 3 timer clock periods to resume, and any
overlapping stop events may be ignored in that interval.
- 4.If the counter is not running
(no start has occurred), a stop event will have no side effects, such as
capturing data.