Interrupt-on-Change and DMA/ADC Triggers

All the Virtual Ports on this device support Interrupt-on-Change. The Interrupt-on-Change feature for PORTW is provided using the IOCWP, IOCWN and IOCWF registers. The logical OR of all the Interrupt-on-Change flags for all the Virtual Ports is available at the system-level as IOCV interrupt as shown in Figure 1 below. See the “IOC – Interrupt-on-Change” chapter for more information.

Figure 1. Interrupt-on-Change for Virtual Port

In addition to the Interrupt-on-Change, the output of each pin of the Virtual Port is also a trigger for the DMA and ADC as shown in the Figure 1. The IOCWP and IOCWN registers are used to select the edge of the virtual output pin transition that generates a trigger.

The following steps are used to configure a virtual pin RWn as a DMA or ADC trigger:
  1. 1.Select the edge that may trigger the DMA/ADC by setting the appropriate bit in the IOCWP and IOCWN registers. Setting IOCWPn bit enables positive edge trigger. Setting the IOCWNn bit enables negative edge trigger. Setting both IOCWPn and IOCWNn bits enable trigger on either edge.
  2. 2.Select the “IOCWFn Flag” as the trigger source in the DMAnSIRQ, DMAnAIRQ, or ADACT registers as appropriate.
See the “Types of Hardware Triggers” section in the “DMA – Direct Memory Access” chapter and the “Auto-Conversion Trigger” section in the “ADC – Analog-to-Digital Converter with Computation Module” chapter for more information.
Important: While the individual IOCWFn Interrupt-on-Change flags are available as triggers to the DMA and ADC modules, there is only one system-level Interrupt-on-Change interrupt source available as IOCV which is the logical OR of all Interrupt-on-Change flags of all the Virtual Ports on the device. This system-level Interrupt-on-Change vector for Virtual Ports (IOCV) is separate and independent from the Interrupt-on-Change vector for I/O ports (IOC). See the “Interrupt Priority” section in the “VIC – Vectored Interrupt Controller Module” chapter for more information.