I3CxDSTAT0

I3CxDSTAT0

Device Status 0

Notes:

1.These are hard-coded read-only bits. This Target module does not support Activity Status, so the ACTMODE bits will always read 0b00.
2.This is a hard-coded read-only bit. This Target module does not support Protocol Error, so the PERR bit will always read ‘0’.
3.This byte is the lower byte read by the Controller during a GETSTATUS CCC.

0x0A9, 0x0DA 8 1index x

I3CxDSTAT0

Bit	7	6	5	4	3	2	1	0
	ACTMODE[1:0]		PERR		INTPEND[3:0]
Access	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Reset	0	0	0		0	0	0	0

Bits 7:6 – ACTMODE[1:0]: Activity Mode (Always read as 0b00)(1)

Activity Mode (Always read as 0b00)⁽¹⁾

The Target’s activity state for monitoring by the Controller.

Bit 5 – PERR: Protocol Error(2)

Protocol Error⁽²⁾

Value	Description
1	The Target detected a protocol error since the last Status read (the bit self-clears after the Controller successfully reads the Target’s status)
0	The Target has not detected a protocol error since the last Status read (Always selected)

Bits 3:0 – INTPEND[3:0]: Pending Interrupt(3)

Pending Interrupt⁽³⁾

Value	Description
other	The interrupt number of the highest priority pending interrupt
0	There is no pending interrupt