CLCnGLS0

CLCnGLS0

CLCn Gate1 Logic Select Register
  0x1AB 8  

CLCnGLS0

Bit  7 6 5 4 3 2 1 0  
  G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  x x x x x x x x  

Bits 1, 3, 5, 7 – G1DyT: dyT: Gate1 Data ‘y’ True (noninverted)

dyT: Gate1 Data ‘y’ True (noninverted)

ValueDescription
1 dyT is gated into g1
0 dyT is not gated into g1

Bits 0, 2, 4, 6 – G1DyN: dyN: Gate1 Data ‘y’ Negated (inverted)

dyN: Gate1 Data ‘y’ Negated (inverted)

ValueDescription
1 dyN is gated into g1
0 dyN is not gated into g1