TUxyPS

TUxyPS

Prescaler Value Register
Notes:
  1. 1.This register needs to only be written when ON = 0.
  2. 2.This register is not available when the module is chained and operated as a Secondary module.
  3. 3.The internal prescaler counter (not the TUxyPS register) is reset by any Stop or Reset event, and upon any write to the TUxyPS and TUxyTMR registers. This allows the next timer interval to be full-length.
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TUxyPS

Bit  7 6 5 4 3 2 1 0  
  PS[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:0 – PS[7:0]: Clock Prescaler Register

Clock Prescaler Register

ValueDescription
0xFF to 0x01 Divider ratio is (PS+1):1
0x00 The input clock is not divided (1:1 clocking)