When enabled (CSD =
0), clock stretching is forced during
buffer read/write operations. This allows the client device time to either load I2CxTXB with
transmit data, or read data from I2CxRXB to clear the buffer. In Client Receive mode, clock stretching prevents receive data overflows. When the first
seven bits of a new byte are received into the receive shift register while I2CxRXB is
full (RXBF =
1), client hardware automatically
stretches the clock and sets CSTR. When the client has read the data in I2CxRXB, client hardware
automatically clears CSTR to release the SCL line and continue communication (see the
figure below).Figure 1. Receive Buffer Clock Stretching
In Client Transmit mode, clock stretching prevents transmit underflows. When I2CxTXB is
empty (TXBE =
1) and the I2CxCNT
register is nonzero (I2CxCNT != 0), client hardware stretches the clock
and sets CSTR upon the 8th falling SCL edge. Once the client has loaded
new data into I2CxTXB, client hardware automatically clears CSTR to release the SCL line
and allow further communication (see the figure below).Figure 2. Transmit Buffer Clock Stretching
