PORTW

PORTW

Virtual Port Output
Notes:
  1. 1.Writes to PORTW update the ‘PORTW write’ register whereas reads come from ‘PORTW read’ register. See Virtual Port Output section for details.
  2. 2.There must be one instruction cycle between write and read of this register, otherwise previous value will be read.
  3. 3.PORTW is not updated when a debug session is active.
  4. 4.This register can only be written when the clock to the module is disabled. See Virtual Port Clock section for details.
  0x499 8  

PORTW

Bit  7 6 5 4 3 2 1 0  
  RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 0, 1, 2, 3, 4, 5, 6, 7 – RWn: Output data for software read of virtual port

Output data for software read of virtual port