The data byte count refers to the number of data bytes in a complete I2C packet. The data byte count does not include address bytes. The I2C Byte Count (I2CxCNT) register is used to specify the length, in bytes, of the complete transaction. The value loaded into I2CxCNT will be decremented by module hardware each time a data byte is transmitted or received by the module.
0
’, the Byte Count
Interrupt Flag (CNTIF) bit is set, and if the Byte Count Interrupt
Enable (CNTIE) is set, the general purpose I2C Interrupt
Flag (I2CxIF) bit of the Peripheral Interrupt Registers (PIR) is also set. If the I2C
Interrupt Enable (I2CxIE) bit of the Peripheral Interrupt Enable (PIE) registers is set,
module hardware will generate an interrupt event.The I2CxCNT register can be read at any time, but it is recommended that a double read is performed to ensure a valid count value.
0
), or after a Stop condition has been
received (Stop Condition Interrupt Flag (PCIF) = 1
). In Host mode, I2CxCNT can be safely written to
any time the Host Data Ready (MDR) or Bus Free (BFRE) bits are set. If the I2C packet is longer than
65,536 bytes, the I2CxCNT register can be updated mid-message to prevent the count from
reaching zero; however, the preventative measures listed above must be followed.0
), the value of the ACKDT bit is used as the acknowledgement response. When I2CxCNT reaches zero
(I2CxCNT = 0
), the value of the Acknowledge End of Count (ACKCNT) bit is used for the acknowledgement response. 0
) and the Restart Enable (RSEN) bit is clear, host hardware automatically generates a Stop condition
upon the 9th falling edge of SCL. When I2CxCNT is clear (I2CxCNT = 0
)
and RSEN is set (RSEN = 1
), host hardware will stretch the clock while
it waits for the Start (S) bit to be set (S = 1
). When the Start bit has been set,
module hardware transmits a Restart condition followed by the address of the client it
wishes to communicate with.