PCON1
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PORVDDIO3 | PORVDDIO2 | RVREG | MEMV | RCM | |||||
| Access | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC | ||||
| Reset | 1 | 1 | 1 | 0 | q |
Configuration Memory Reset Flag
| Value | Description |
|---|---|
| 1 | A Reset occurred due to corruption of the configuration and/or calibration data latches |
| 0 | The configuration and calibration latches have not been corrupted |
Memory Violation Reset Flag
| Value | Description |
|---|---|
| 1 | No
memory violation Reset occurred or set to ‘1’ by
firmware |
| 0 | A
memory violation Reset occurred (set to ‘0’ in hardware
when a Memory Violation occurs) |
Main LDO Voltage Regulator Reset Flag
| Value | Description |
|---|---|
| 1 | No LDO
or ULP “ready” Reset has occurred or set to ‘1’ by
firmware |
| 0 | LDO or ULP “ready” Reset has occurred (VDDCORE reached its minimum spec) |
MVIO VDDIO2 Reset Flag
| Value | Description |
|---|---|
| 1 | No
VDDIO2 Power-on Reset occurred or set to ‘1’
by firmware |
| 0 | A VDDIO2 Power-on Reset occurred (set to
‘0’ in hardware when a DDIO2 Power-on Reset
occurs) |
MVIO VDDIO3 Reset Flag
| Value | Description |
|---|---|
| 1 | No
VDDIO3 Power-on Reset occurred or set to ‘1’
by firmware |
| 0 | A VDDIO3 Power-on Reset occurred (set to
‘0’ in hardware when a DDIO3 Power-on Reset
occurs) |