The Universal Timer module provides three interrupt sources – Period
Register match, Zero and Capture.
- 1.A PR match interrupt occurs and the
PRIF interrupt flag in the TUxyCON1 register
is set when the TUxyTMR counter register increments and becomes equal to the TUxyPR
period register. The PRIF interrupt will not occur if the user writes the PR value
to the TUxyTMR counter register directly.
- 2.A zero interrupt occurs and the ZIF interrupt flag in the TUxyCON1 register is
set when the TUxyTMR counter register becomes equal to zero. This occurs when:
- A Reset condition resets the counter to zero, or
- Software sets the CLR command bit, or
- Counter naturally overflows to zero, or
- User writes zero to the
TUxyTMR counter register directly
- 3.A capture interrupt occurs and the
CIF interrupt flag in the TUxyCON1 register is
set whenever a capture event occurs, and the TUxyCR capture register is updated with
the counter value. See Timer Counter and Capture Registers for a list
of capture event conditions. The CIF interrupt trigger requires a running
timer.
Each interrupt has a corresponding enable bit (
PRIE,
ZIE and
CIE) in the TUxyCON0 register. Setting any of the three interrupt enable
bits will allow the module to generate a corresponding interrupt. The interrupt flags
(
PRIF,
ZIF and
CIF) will set even if the corresponding interrupt is disabled.
All the three interrupt flags are combined together to form one single, top system level
TUxyIF interrupt flag in the PIRx register, as shown in Figure 1. The TUxyIF interrupt flag is a read-only bit in the PIRx register,
which is automatically cleared when all the three interrupt flags (PRIF, ZIF and CIF)
are cleared.
The Universal Timer module also provides the three interrupt sources to
trigger DMA transfers (PRIF, ZIF and CIF conditions). The TUxyPR period register is also
double-buffered to facilitate DMA loading of the register in response to a CIF interrupt
trigger.
Important:
- 1.The interrupts need not be
enabled with their associated enable bits to be used as triggers for DMA
transfer.
- 2.The interrupts must be
enabled for the TUxyIF flag to be set in the PIRx register as shown in Figure 1.
Figure 1. Interrupt and DMA Trigger