SPI Control Register 2(3)

  1. 1.The BUSY bit is subject to synchronization delay of up to two instruction cycles. The user must wait after loading the transmit buffer (the SPIxTXB register) before using it to determine the status of the SPI module.
  2. 2.See the Host Mode TXR/RXR Settings table as well as the Host Mode and Client Mode sections for more details pertaining to TXR and RXR function.
  3. 3.This register will not be written to while a transfer is in progress (the BUSY bit is set).
  0x01DD 8   1 1 x


Bit  7 6 5 4 3 2 1 0  
Access  R R       R/W R/W R/W  
Reset  0 0       0 0 0  

Bit 7 – BUSY: SPI Module Busy Status(1)

SPI Module Busy Status(1)

1 Data exchange is busy
0 Data exchange is not taking place

Bit 6 – SSFLT: SS_in Fault Status

SS_in Fault Status

x SSET = 1 This bit is unchanged
1 SSET = 0 SS_in ended the transaction unexpectedly, and the data byte being received was lost
0 SSET = 0 SS_in ended normally

Bit 2 – SSET: Client Select Enable

Client Select Enable

1 Host SS_out is driven to the Active state continuously
0 Host SS_out is driven to the Active state while the transmit counter is not zero
1 Client SS_in is ignored and data is clocked on all SCK_in (as though SS = TRUE at all times)
0 Client SS_in enables/disables data input and tri-states SDO if the TRIS bit associated with the SDO pin is set (see the Client Mode Transmit table for details)

Bit 1 – TXR: Transmit Data-Required Control(2)

Transmit Data-Required Control(2)

1 TxFIFO data is required for a transfer
0 TxFIFO data is not required for a transfer

Bit 0 – RXR: Receive FIFO Space-Required Control(2)

Receive FIFO Space-Required Control(2)

1 Data transfers are suspended when RxFIFO is full
0 Received data is not stored in the FIFO