TxCON

TxCON

Timerx Control Register

Note:
  1. 1.In certain modes, the ON bit will be auto-cleared by hardware. See Table 1.
  0x11B,0x121 8   2,4 x

TxCON

Bit  7 6 5 4 3 2 1 0  
  ON CKPS[2:0] OUTPS[3:0]  
Access  R/W/HC R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bit 7 – ON: Timer On(1)

Timer On(1)

ValueDescription
1

Timer is on

0

Timer is off: All counters and state machines are reset

Bits 6:4 – CKPS[2:0]: Timer Clock Prescale Select

Timer Clock Prescale Select

ValueDescription
111

1:128 Prescaler

110

1:64 Prescaler

101

1:32 Prescaler

100

1:16 Prescaler

011

1:8 Prescaler

010

1:4 Prescaler

001

1:2 Prescaler

000

1:1 Prescaler

Bits 3:0 – OUTPS[3:0]: Timer Output Postscaler Select

Timer Output Postscaler Select

ValueDescription
1111

1:16 Postscaler

1110

1:15 Postscaler

1101

1:14 Postscaler

1100

1:13 Postscaler

1011

1:12 Postscaler

1010

1:11 Postscaler

1001

1:10 Postscaler

1000

1:9 Postscaler

0111

1:8 Postscaler

0110

1:7 Postscaler

0101

1:6 Postscaler

0100

1:5 Postscaler

0011

1:4 Postscaler

0010

1:3 Postscaler

0001

1:2 Postscaler

0000

1:1 Postscaler