Clock-to-Data Turnaround Time

Clock-to-Data Turnaround Time (TSCO) is the time duration between reception of an SCL edge by the Target and the start of driving an SDA change as shown in Figure 1 below. It is the measurement of the total internal delay from the SCL input to the SDA output in the Target, not including factors such as bus capacitance and path delay which are included in the broader computation. The MIPI I3C® Specification requires a maximum Clock-to-Data turnaround delay of 12 ns. This Target module can meet this specification with both the buffers (I3C Low-Voltage Buffer and Schmitt Trigger Buffer) across the entire I3C operating voltage range.

Figure 1. Clock-to-Data Turnaround Time