SDO Drive/Tri-State

The TRIS bit associated with the SDO pin controls whether the SDO pin will tri-state. When this TRIS bit is cleared, the pin will always be driving to a level, even when the SPI module is inactive. When the SPI module is inactive (either due to the host not clocking the SCK line or the SS being false), the SDO pin will be driven to the value of the LAT bit associated with the SDO pin. When the SPI module is active, its output is determined by both TXR and whether there is data in the transmit FIFO.

When the TRIS bit associated with the SDO pin is set, the pin will only have an output level driven to it when TXR = 1 and the Client Select input is true. In all other cases, the pin will be tri-stated.

Table 1. Client Mode Transmit
TRISxn(1) TXR SS TXBE SDO State
0 0 FALSE 0 Output level determined by LATxn(2)
0 0 FALSE 1 Output level determined by LATxn(2)
0 0 TRUE 0

Outputs the oldest byte in the TXFIFO.
Does not remove data from the TXFIFO.

0 0 TRUE 1 Outputs the most recently received byte
0 1 FALSE 0 Output level determined by LATxn(2)
0 1 FALSE 1 Output level determined by LATxn(2)
0 1 TRUE 0

Outputs the oldest byte in the TXFIFO.
Removes transmitted byte from the TXFIFO.
Decrements occupancy of TXFIFO.

0 1 TRUE 1

Outputs the most recently received byte.
Sets the TXUIF bit.

1 0 FALSE 0 Tri-stated
1 0 FALSE 1 Tri-stated
1 0 TRUE 0 Tri-stated
1 0 TRUE 1 Tri-stated
1 1 FALSE 0 Tri-stated
1 1 FALSE 1 Tri-stated
1 1 TRUE 0

Outputs the oldest byte in the TXFIFO.
Removes transmitted byte from the TXFIFO.
Decrements occupancy of TXFIFO.

1 1 TRUE 1

Outputs the most recently received byte.
Sets the TXUIF bit

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Notes:
  1. 1.TRISxn is the bit in the TRISx register corresponding to the pin that SDO has been assigned with PPS.
  2. 2.LATxn is the bit in the LATx register corresponding to the pin that SDO has been assigned with PPS.