Bus Idle Condition

The Bus Idle condition is defined as a period during which the Bus Available condition is sustained continuously for a duration of at least 200 µs(1). This time is specified by the user using the I3CxBIDL Bus Idle Condition Threshold Register. An internal counter incremented by the I3CxCLK clock is compared against the value in the I3CxBIDL register to determine when a Bus Idle condition occurs. This counter stops counting at the I3CxBIDL value and resets at every Stop condition.

For example, for I3CxCLK = FOSC = 64 MHz, a 200 µs duration takes 12,800 counts. Hence, the user must set I3CxBIDL = 12800 during setup for I3C to operate as expected. Table 1 below contains I3CxBIDL values for commonly used I3CxCLK clock speeds for reference.

The Bus Idle condition is key to ensuring bus stability when new devices are added to the bus during Hot-Join events.

CAUTION: The user must set appropriate values in the I3CxBAVL and I3CxBIDL registers during setup to match the I3C bus condition timings for the module to operate as expected. Failing to do so will result in unexpected behavior.
Important:
  1. 1.The duration of Bus Free, Bus Available, and Bus Idle conditions are as per Timing Specifications in the MIPI I3C® Specification Basic 1.0.
Table 1. I3CxBAVL and I3CxBIDL Values for Commonly Used I3CxCLK Clock Speeds
I3CxCLK Clock Speed I3CxBAVL Value for 1 µs I3CxBIDL Value for 200 µs
2 MHz 2 400
8 MHz 8 1600
16 MHz 16 3200
32 MHz 32 6400
64 MHz 64 12800
Figure 1. I3C® Bus Conditions
Parent topic: I3C Bus Conditions