Overview

The MVIO feature allows a subset of the I/O pins to be powered by a different I/O voltage domain than the rest of the I/O pins. This eliminates the need of having external level shifters for communication or control of external components running on a different voltage level. The MVIO-capable I/O pads are supplied by a voltage applied to the VDDIOx power pin(s), while the regular I/O pins are supplied by the voltage applied to the VDD (also known as VDDIO) device power pin(s).

The MVIO can be configured in one of the two supply modes:

• Single Supply mode, where the MVIO pins are powered at the same voltage level as the non-MVIO pins. This turns off the internal voltage comparator, thus reducing current consumption. The user must connect the VDDIOx pin(s) to the VDD pin(s).
• Dual Supply mode where the MVIO pins are supplied by the VDDIOx voltage, which may be different from the voltage supplied to the VDD pin.
The VDDIOxMD configuration bit determines the MVIO Supply mode. Setting VDDIOxMD bit to 0 in the appropriate CONFIGx register selects the Single Supply mode, whereas setting VDDIOxMD to 1 selects the Dual Supply mode. The loss or gain of power on the VDDIOx power pin(s) is signaled by the VDDIOxRDY bit in the MVIOSTAT status register. This status bit has a corresponding VDDIOx interrupt as well. Refer to Interrupts and DMA Triggers for more information.

The MVIO pins on the VDDIOx power domain are capable of the same digital behavior as regular I/O pins like GPIO, serial communication, and PPS functionality. However, the MVIO pins do not support analog inputs or outputs. The MVIO pins on this device are equipped with I3C Low Voltage Buffers in addition to regular Schmitt Trigger and TTL buffers. The input Schmitt Trigger levels are scaled according to the VDDIOx supply voltage, whereas the I3C Low-Voltage Buffers are operational below the minimum VDDIOx supply voltage down to 1V. Refer to Power Sequencing for more information. The pins associated with the MVIO voltage domain are shown in the “Pin Diagrams” and “Pin Allocation Tables” chapters of the data sheet.

A divided-down voltage is available as input to the ADC as well to monitor voltage levels on this voltage domain. Refer to the Voltage Measurement section for more information.

The MVIO uses a cross-reference approach to checking whether the voltage levels are within the operational range using the two built-in voltage monitors as shown in Figure 1. The first monitor uses VDD as the reference voltage and checks to make sure that VDDIOx is higher than the minimum MVIO voltage. It uses the device’s Power-On Reset (POR) circuit to ensure that VDD itself is of sufficient voltage before level shifting data to the other domain. The second monitor uses VDDIOx as the reference voltage and checks to make sure that VDD is higher than the device’s minimum operating voltage. It has a separate in-built POR circuit that ensures that VDDIOx itself is of sufficient voltage before level shifting data to the other domain. This ensures reliable data communication between the two domains. The internal level translators between the two domains eliminate the need for external voltage level translators. Refer to the Power Sequencing section for more information.

Table 1. Operating Voltage Range for MVIO Domains
Power Domain Voltage Range
VDD Power Domain 1.8V – 5.5V
VDDIOx Power Domain

1.62V – 3.6V (I3C Enabled)

1.62V – 5.5V (I3C Disabled)

Notes:
1. 1.The VDDIOx supply voltage can ramp up and down independently of VDD supply voltage.
2. 2.The VDDIOx supply voltage can go below the device’s minimum VDD of 1.8V. However, the VDD must be within the operational range for the device to be functional.
3. 3.The MVIO pins on VDDIOx power domain are equipped with I3C Low Voltage Buffers to support I3C communications at voltages down to 1V. Refer to Power Sequencing for more information.