If there is no activity on the SCL line and the Target is not in its Idle state
(in-between transactions), then it is possible that either the Controller or the Target
might have stalled during a transaction. As a preventive measure for the stalled Target
device from hanging indefinitely, an internal bus time-out timer will start counting and
reset the Target module once it expires. This time is specified by the user using the
I3CxBTO
Bus Time-out Register. An internal counter incremented by the
I3CxCLK clock
is compared against the value in the I3CxBTO register to determine when a bus time-out
occurs and to reset the Target module. This feature is disabled by default and must be
enabled by setting the Bus Time-out Enable
BTOEN bit.
It is recommended to set the bus time-out value to at least 32 times the SCL period,
however it is up to the user’s discretion to choose a value based on the application
speed. For example, for FSCL = 12.5 MHz, 32 times of SCL period results in a
bus time-out of 2.56 µs. For I3CxCLK = FOSC = 64 MHz, a 2.56 µs duration
takes 164 counts. Hence, the user must set I3CxBTO = 164 during setup.
Important: When the Target module
is being used in I
2C/SMBus mode (
OPMD =
0b00
), this feature can be utilized to program an
SMBus Time-out period. The SMBus protocol dictates a bus time-out of 25 ms duration for
Target devices.
Once the time-out occurs, the
BTOIF Bus Time-out Error Interrupt Flag is set. The value in the
I3CxBRST
register determines the duration of the Bus Time-out Reset. An internal counter
incremented by the clock select using the I3CxCLK is compared against the value in the
I3CxBRST register to determine how long the SCL Hang Reset lasts.
The Bus Time-out Reset is a soft Reset of the Target module. Unlike the Software Reset
mentioned above, the Bus Time-out Reset only resets the internal states of the Target
module and its associated status registers while preserving the control register
configurations.
The following registers are reset following a Bus Time-out Reset:
- Data Registers: I3CxRXB and
I3CxTXB
- Status Registers: I3CxSTAT and
I3CxBSTAT
- Address Registers: I3CxDADR
- CCC Registers: I3CxEC, I3CxMWL,
I3CxMRL, I3CxIBIPSZ, I3CxRSTACT, and I3CxUNKNCCC
The following registers do not reset following a Bus Time-out Reset:
- Control Registers: I3CxCON,
I3CxRETRY, I3CxFEAT, I3CxI2CCON, and IOLVCON
- Interrupt Registers: I3CxPIRx,
I3CxERRIRx, I3CxPIEx, and I3CxERRIEx
- Timing Registers: I3CxCLK, I3CxBIDL,
I3CxBAVL, I3CxBTO, and I3CxBRST
- Address Registers: I3CxSADR
- CCC Registers: I3CxIBIMB, I3CxPIDx,
I3CxBCR, I3CxDCR, I3CxMWS, I3CxMRS, I3CxMRT, and I3CxDSTATx
While the Bus Time-out Reset preserves the Static Address of the Target, it clears the
assigned Dynamic Address. To obtain a Dynamic Address again, the Target can perform a
Hot-Join
request or wait for the Controller to Enter Dynamic Address Assignment mode using the
ENTDAA
CCC.