Fail-Safe Clock Monitor Fault Injection

Each of the Fail-Safe Clock monitors on this device has its own respective Fault Injection bit. The Fault Injection bit is used to verify in software that the FSCM functions work properly and will detect a clock failure during normal operation. If the FSCM Fault Injection bit is set, the FSCM sample clock input will be blocked, forcing a clock failure. Writing to the FOSC FSCM Fault Injection (FSCMFFI) bit will result in the system clock switching to HFINTOSC and the FSCMFEV bit will be set as well as the Oscillator Fail Interrupt Flag (OSFIF) of the PIR registers. Writing to the primary and secondary external FSCM Fault Injection (FSCMPFI and FSCMSFI) bits will result in the respective FSCM Fault Status (FSCMPEV and FSCMSEV) bits being set but the system clock will not switch. Additionally, the Oscillator Fail Interrupt Flag (OSFIF) of the PIR registers will also be set.