The specific Reset level is identified by the Defining Byte that is sent along with the Direct or Broadcast Write RSTACT CCC. The defining byte is stored in the I3CxRSTACT register. Refer to Table 1 in the definition of RSTACT CCC for a list of all the available configuration options.
The I3CxRSTACT register is initialized to 0xFF
upon Reset. Once the
Target receives the RSTACT CCC, it configures itself for the upcoming Target Reset
Pattern as explained below. The I3CxRSTACT register is updated with the defining byte of
the RSTACT CCC which allows the user software to perform additional actions.
0xFF
to it.When the Target receives a Target Reset Pattern immediately following the RSTACT CCC, the Target performs the configured Reset action based on the I3CxRSTACT Defining Byte values as mentioned in Table 1. To be fully compliant with the I3C protocol, it is recommended for the user software to perform additional actions as outlined in Table 1.
Refer to Pseudo-code for Target Reset Pattern Detection below to learn more about using user software in conjunction with the different levels of Target Reset actions.
I3CxRSTACT Defining Byte | Level of Reset | Action Performed by Target Upon Receiving Target Reset Pattern | Recommended User Action (1) |
---|---|---|---|
0x00 |
No Target Reset | No Reset action performed | Nothing |
0x01 |
Reset I3C Target Module | The Target returns to its Idle state, lets go of the I3C bus and ignores all traffic until the next Bus Idle condition. All the register configurations, Static and Dynamic Addresses are kept intact, thus performing a soft Reset of the I3C Target module. | Perform a Software Reset of the Target module as outlined in Software Target Reset |
0x02 |
Reset Entire Target Device | Perform a system level Reset of the entire device. Refer to
“RESET Instruction” section in the
“Resets” chapter. |
|
Note:
|
inline void I3C1_Target_SoftwareReset()
{
// Perform software Reset
I3C1CONbits.RST = 1;
// Wait for software Reset to complete
while(I3C1CONbits.RST); // RST bit clears upon Reset completion
}
void I3C1_Target_Reset_ISR()
{
// This ISR is executed when PIRx.I3C1RIF is set
// Target Reset Pattern detected on bus
// Counter to count number of non-RSTACT Reset patterns (static)
static uint8_t count = 0;
// First, clear the flag to re-arm
PIRxbits.I3C1RIF = 0; // x = appropriate PIR register
// Check status of RSTACT CCC Defining Byte
// RSTACT DB 0x00 ==> No Reset
// RSTACT DB 0x01 ==> I3C peripheral Reset
// RSTACT DB 0x02 ==> Whole chip Reset
if(I3C1RSTACT == 0x00) {
// Reset counter and do nothing
count = 0;
}
else if(I3C1RSTACT == 0x01) {
// Target is already in Idle state by now
// Suggested user action is to reset the I3C module
count = 0; // Reset counter
I3C1_Target_SoftwareReset();
}
else if(I3C1RSTACT == 0x02) {
// Target is already in Idle state by now
// Suggested user action is to reset the entire device
count = 0; // Reset counter
RESET();
}
else if(I3C1RSTACT == 0xFF) {
// Target Reset Pattern detected without any preceeding RSTACT CCC
if(count == 0) {
// Reset Pattern detected w/o RSTACT for the first time
// Suggested user action is to reset the I3C module
count++; // Increment counter
I3C1_Target_SoftwareReset();
}
else if(count > 0) {
// Reset Pattern detected w/o RSTACT for the second time
// Suggested user action is to reset the whole device
count = 0; // Reset counter
RESET();
}
}
// Reset RSTACT CCC Defining Byte to default value for future detection
I3C1RSTACT = 0xFF;
}