I2CxCON2

I2CxCON2

I2C Control Register 2
0x01E8 8         1 1 x
Parent topic: Register Definitions: I2C Control

I2CxCON2

Bit  7 6 5 4 3 2 1 0  
  ACNT GCEN   ABD SDAHT[1:0] BFRET[1:0]  
Access  R/W R/W   R/W R/W R/W R/W R/W  
Reset  0 0   0 0 0 0 0  

Bit 7 – ACNT: Auto-Load I2C Count Register Enable

Auto-Load I2C Count Register Enable

ValueDescription
1 The first transmitted/received byte after the address is automatically loaded into the I2CxCNT register
0 Auto-load of I2CxCNT is disabled

Bit 6 – GCEN: General Call Address Enable (used when MODE I2C Mode Select = 00x or MODE = 11x)

General Call Address Enable (used when MODE = 00x or MODE = 11x)

ValueDescription
1 General Call Address (0x00) causes an address match event
0 General Call addressing is disabled

Bit 4 – ABD: Address Buffer Disable

Address Buffer Disable

ValueDescription
1 Address buffers are disabled.

Received address is loaded into I2CxRXB, address to transmit is loaded into I2CxTXB.
0 Address buffers are enabled.

Received address is loaded into I2CxADB0/I2CxADB1, address to transmit is loaded into I2CxADB0/I2CxADB1.

Bits 3:2 – SDAHT[1:0]: SDA Hold Time Selection

SDA Hold Time Selection

ValueDescription
11 Reserved
10 Minimum of 30 ns hold time on SDA after the falling SCL edge
01 Minimum of 100 ns hold time on SDA after the falling SCL edge
00 Minimum of 300 ns hold time on SDA after the falling SCL edge

Bits 1:0 – BFRET[1:0]: Bus Free Time Selection

Bus Free Time Selection

ValueDescription
11 64 I2CxCLK pulses
10 32 I2CxCLK pulses
01 16 I2CxCLK pulses
00 8 I2CxCLK pulses