Bus Available Condition

The Bus Available condition is defined as the period during which the Bus Free condition is sustained continuously for a duration of at least 1 µs(1). This time is specified by the user using the I3CxBAVL Bus Available Condition Threshold Register. An internal counter incremented by the I3CxCLK clock is compared against the value in the I3CxBAVL register to determine when a Bus Available condition occurs. This counter stops counting at the I3CxBAVL value and resets at every Stop condition.

For example, for I3CxCLK = FOSC = 64 MHz, a 1 µs duration will require 64 counts. Therefore, the user must set I3CxBAVL = 64 during setup for I3C to operate as expected. Table 1 below contains I3CxBAVL values of commonly used I3CxCLK clock speeds for reference.

The Bus Available condition ensures that the bus is stable for events that require address arbitration, like Dynamic Address Assignment and In-Band Interrupts.