I2C Operation

All I2C communication is performed in 9-bit segments consisting of an 8-bit address/data segment followed by a 1-bit acknowledgement segment. Address and data bytes are transmitted with the Most Significant bit (MSb) first. Interaction between the I2C module and other devices on the bus is controlled and monitored through several I2C Control, Status, and Interrupt registers.

To begin any I2C communication, mater hardware checks to ensure that the bus is in an Idle state as indicated by the Bus Free Status (BFRE) bit. When BFRE = 1, both SDA and SCL lines are floating to a logic high and the bus is considered Idle. When the host detects an Idle bus, it transmits a Start condition, followed by the address of the client it intends to communicate with. The client address can be either 7-bit or 10-bit, depending on the application design.

In 7-bit Addressing mode, the Least Significant bit (LSb) of the 7-bit client address is reserved for the Read/not Write (R/W) bit, while in 10-bit Addressing mode, the LSb of the high address byte is reserved as the R/W bit. If the R/W bit is clear (R/W = 0), the host intends to read information from the client. If R/W is set (R/W = 1), the host intends to write information to the client. If the addressed client exists on the bus, it must respond with an Acknowledgement (ACK) sequence.

Once a client has been successfully addressed, the host will continue to receive data from the client, write data to the client, or a combination of both. Data is always transmitted Most Significant bit (MSb) first. When the host has completed its transactions, it can either issue a Stop condition, signaling to the client that communication is to be terminated, or a Restart condition, informing the bus that the current host wishes to hold the bus to communicate with the same or other client devices.