Standard Instruction Set

The standard PIC18 instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are a few instructions that require two- or three-program memory locations.

Each single-word instruction is a 16-bit word divided into an opcode that specifies the instruction type and one or more operands, which further specifies the operation of the instruction.

The instruction set is highly orthogonal and is grouped into four basic categories:

The PIC18 instruction set summary in Table 2 lists byte-oriented, bit-oriented, literal and control operations. Table 1 shows the opcode field descriptions.

Most byte-oriented instructions have three operands:

The file register designator ‘f’ specifies which file register is to be used by the instruction. The destination designator ‘d’ specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is placed in the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction.

All bit-oriented instructions have three operands:

The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register designator ‘f’ represents the number of the file in which the bit is located.

The literal instructions may use some of the following operands:

The control instructions may use some of the following operands:

All instructions are a single word, except for a few two- or three-word instructions. These instructions were made two- or three-word to contain the required information in 32 or 48 bits. In the second and third words, the four MSbs are ‘1’s. If this second or third word is executed as an instruction (by itself), it will execute as a NOP.

All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the Program Counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP.

The two-word instructions execute in two instruction cycles and three-word instructions execute in three instruction cycles.

One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 μs. If a conditional test is true, or the Program Counter is changed as a result of an instruction, the instruction execution time is 2 μs. Two-word branch instructions (if true) take 3 μs.

Figure 1, Figure 2 and Figure 3 show the general formats that the instructions can have. All examples use the convention ‘nnh’ to represent a hexadecimal number.

The Instruction Set Summary, shown in Table 2, lists the standard instructions recognized by the Microchip MPASMTM Assembler.

Standard Instruction Set provides a description of each instruction.

Table 1. Opcode Field Descriptions
Field Description
a

RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register (default)

ACCESS ACCESS = 0: RAM access bit symbol
BANKED BANKED = 1: RAM access bit symbol
bbb Bit address within an 8-bit file register (0 to 7)
BSR Bank Select Register (BSR). Used to select the current RAM bank.
d

Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f (default)

dest Destination: either the WREG register or the specified register file location
f 8-bit register file address (00h to FFh)
fn FSR Number (0 to 2)
fs 12-bit register file address (000h to FFFh) or 14-bit register file address (0000h to 3FFFh). This is the source address.
fd 12-bit register file address (000h to FFFh) or 14-bit register file address (0000h to 3FFFh). This is the destination address.
zs 7-bit literal offset for FSR2 to used as register file address (000h to FFFh). This is the source address.
zd 7-bit literal offset for FSR2 to used as register file address (000h to FFFh). This is the destination address.
k Literal field, constant data or label (may be either a 6-bit, 8-bit, 12-bit or a 20-bit value)
label Label name

mm

*

*+

*-

+*

The mode of the TBLPTR register for the table read and table write instructions.
 Only used with table read and table write instructions:

No change to register (such as TBLPTR with table reads and writes)

Post-Increment register (such as TBLPTR with table reads and writes)

Post-Decrement register (such as TBLPTR with table reads and writes)

Pre-Increment register (such as TBLPTR with table reads and writes)

n The relative address (two’s complement number) for relative branch instructions, or the direct address for call/branch and return instructions.
PRODH Product of multiply high byte
PRODL Product of multiply low byte
s

Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers (default)
s = 1: certain registers loaded into/from shadow registers (Fast mode)

u Unused or unchanged
W W = 0: Destination select bit symbol
WREG Working register (accumulator)
x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.
TBLPTR 21-bit Table Pointer (points to a program memory location)
TABLAT 8-bit table latch
TOS Top-of-stack (TOS)
PC Program Counter
PCL Program Counter low byte
PCH Program Counter high byte
PCLATH Program Counter high byte latch
PCLATU Program Counter upper byte Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer
TO Time-Out bit
PD Power-Down bit
C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative
{ } Optional argument
[ ] Indexed address
( ) Contents
< > Register bit field
[expr]<n> Specifies bit n of the register indicated by pointer expr
Assigned to
In the set of
italics User defined term (font is Courier)
Figure 1. General Format for Byte-Oriented Instructions
Figure 2. General Format for Bit-Oriented and Literal Instructions
Figure 3. General Format for Control Instructions
Table 2. Standard Instruction Set
Mnemonic,

Operands

Description Cycles 16-Bit Instruction Word Status

Affected

Notes
MSb     LSb
BYTE-ORIENTED FILE REGISTER INSTRUCTIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1
ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1
CLRF f, a Clear f 1 0110 101a ffff ffff Z  
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1
MOVF f, d, a Move f to WREG or f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (12-bit source)

to fd (12-bit destination)

2 1100 fsfsfsfs fsfsfsfs fsfsfsfs None 1, 3, 4
1111 fdfdfdfd fdfdfdfd fdfdfdfd
MOVFFL fs, fd Move fs (14-bit source)

to fd (14-bit destination)

3 0000 0000 0110 fsfsfsfs None 1, 3
1111 fsfsfsfs fsfsfsfs fsfsfdfd
1111 fdfdfdfd fdfdfdfd fdfdfdfd
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None  
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N 1
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N 1
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N 1
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N 1
SETF f, a Set f 1 0110 100a ffff ffff None  
SUBFWB f, d, a Subtract f from WREG with 
Borrow 1 0101 01da ffff ffff C, DC, Z, OV, N 1
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1
SUBWFB f, d, a Subtract WREG from f with Borrow 1 0101 10da ffff ffff C, DC, Z, OV, N 1
SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 1
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N 1
BYTE-ORIENTED SKIP INSTRUCTIONS
CPFSEQ f, a Compare f with WREG, skip if = 1 – 4 0110 001a ffff ffff None 1, 2
CPFSGT f, a Compare f with WREG, skip if > 1 – 4 0110 010a ffff ffff None 1, 2
CPFSLT f, a Compare f with WREG, skip if < 1 – 4 0110 000a ffff ffff None 1, 2
DECFSZ f, d, a Decrement f, Skip if 0 1 – 4 0010 11da ffff ffff None 1, 2
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 – 4 0100 11da ffff ffff None 1, 2
INCFSZ f, d, a Increment f, Skip if 0 1 – 4 0011 11da ffff ffff None 1, 2
INFSNZ f, d, a Increment f, Skip if Not 0 1 – 4 0100 10da ffff ffff None 1, 2
TSTFSZ f, a Test f, skip if 0 1 – 4 0110 011a ffff ffff None 1, 2
BIT-ORIENTED FILE REGISTER INSTRUCTIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1
BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1
BIT-ORIENTED SKIP INSTRUCTIONS
BTFSC f, b, a Bit Test f, Skip if Clear 1 – 4 1011 bbba ffff ffff None 1, 2
BTFSS f, b, a Bit Test f, Skip if Set 1 – 4 1010 bbba ffff ffff None 1, 2
CONTROL INSTRUCTIONS
BC n Branch if Carry 1 – 2 1110 0010 nnnn nnnn

None

2
BN n Branch if Negative 1 – 2 1110 0110 nnnn nnnn

None

2
BNC n Branch if Not Carry 1 – 2 1110 0011 nnnn nnnn

None

2
BNN n Branch if Not Negative 1 – 2 1110 0111 nnnn nnnn

None

2
BNOV n Branch if Not Overflow 1 – 2 1110 0101 nnnn nnnn

None

2
BNZ n Branch if Not Zero 1 – 2 1110 0001 nnnn nnnn

None

2
BOV n Branch if Overflow 1 – 2 1110 0100 nnnn nnnn

None

2
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn

None

2
BZ n Branch if Zero 1 – 2 1110 0000 nnnn nnnn

None

2
CALL k, s Call subroutine 2 1110 110s kkkk kkkk

None

2, 3
1111 kkkk kkkk kkkk
CALLW Call subroutine using WREG 2 0000 0000 0001 0100 None 2
GOTO k Go to address 2 1110 1111 kkkk kkkk None 3
1111 kkkk kkkk kkkk
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None 2
RETFIE s Return from interrupt enable 2 0000 0000 0001 000s INTCONx STAT bits 2
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None 2
RETURN s Return from Subroutine 2 0000 0000 0001 001s None 2
INHERENT INSTRUCTIONS
CLRWDT Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD  
DAW Decimal Adjust WREG 1 0000 0000 0000 0111 C  
NOP No Operation 1 0000 0000 0000 0000 None  
NOP No Operation 1 1111 xxxx xxxx xxxx None 3
POP

Pop top of return stack (TOS) 1 0000 0000 0000 0110 None  
PUSH Push top of return stack (TOS) 1 0000 0000 0000 0101 None  
RESET Software device Reset 1 0000 0000 1111 1111 All  
SLEEP Go into Standby mode 1 0000 0000 0000 0011 TO, PD  
LITERAL INSTRUCTIONS
ADDFSR fn, k Add FSR (fn) with literal (k) 1 1110 1000 fnfnkk kkkk None  
ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N  
ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N  
IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N  
LFSR fn, k Load FSR(fn) with a 14-bit literal (k) 2 1110 1110 00fnfn kkkk None 3
1111 00kk kkkk kkkk
MOVLB k Move literal to BSR<5:0> 1 0000 0001 00kk kkkk None  
MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None  
MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None  
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None  
SUBFSR fn, k Subtract literal (k) from FSR (fn) 1 1110 1001 fnfnkk kkkk None  
SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N  

XORLW

k

Exclusive OR literal with WREG

1

0000 1010 kkkk kkkk

Z, N

 
DATA MEMORY – PROGRAM MEMORY INSTRUCTIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None  
TBLRD*+ Table Read with post-increment 2 0000 0000 0000 1001 None  
TBLRD*- Table Read with post-decrement 2 0000 0000 0000 1010 None  
TBLRD+* Table Read with pre-increment 2 0000 0000 0000 1011 None  
TBLWT* Table Write 2 0000 0000 0000 1100 None  
TBLWT*+ Table Write with post-increment 2 0000 0000 0000 1101 None  
TBLWT*- Table Write with post-decrement 2 0000 0000 0000 1110 None  
TBLWT+* Table Write with pre-increment 2 0000 0000 0000 1111

None

 
Notes:
  1. 1.When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’.
  2. 2.If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
  3. 3.Some instructions are multi-word instructions. The extra words of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
  4. 4.fs and fd do not cover the full memory range. 2 MSbs of bank selection are forced to 0b00 to limit the range of these instructions to the lower 4k addressing space.