I3CxI2CCON

I3CxI2CCON

I3C Legacy I2C Control

Note: These bits are intended to support the Legacy I2C operation, but are effective regardless of the current operating status reflected in the OPMD bits. Enabling these bits while the module is operating in I3C SDR mode (OPMD = 0b01) will cause the module to become incompatible with the I3C Specification.
0x0B2, 0x0E3 8     1index x
Parent topic: Register Definitions: I3C Control

I3CxI2CCON

Bit  7 6 5 4 3 2 1 0  
            FLTEN SDAHT[1:0]  
Access            R/W R/W R/W  
Reset            0 0 0  

Bit 2 – FLTEN: Spike Filter Enable bit

Spike Filter Enable bit

ValueDescription
1 50 ns Spike Filters on SCL and SDA are enabled
0 50 ns Spike Filters on SCL and SDA are disabled

Bits 1:0 – SDAHT[1:0]: SDA Hold Time Selection bits

SDA Hold Time Selection bits

ValueDescription
11 Minimum 300 ns hold time on SDA after falling edge of SCL
10 Minimum 100 ns hold time on SDA after falling edge of SCL
01 Minimum 30 ns hold time on SDA after falling edge of SCL
00 No hold time on SDA after falling edge of SCL