When the system clock (F
OSC) fails, the Oscillator Fail Interrupt Flag (OSFIF)
bit of the PIR registers will be set, as well as the corresponding FSCM
failure status (FSCMFEV) bit. If the Oscillator Fail Interrupt Enable
(OSFIE) bit was set, an interrupt will be generated when OSFIF is high. If
enabled, the F
OSC Fail-Safe Clock Monitor will switch the system
clock to HFINTOSC when a failure is detected by overwriting the
NOSC/
COSC bits. The frequency of HFINTOSC will
depend on the previous state of the
FRQ bits and the state of the
NDIV/
CDIV bits. Once a failure is detected, software
can be used to take steps to mitigate the repercussions of the oscillator
failure. The FSCM will switch the system clock to HFINTOSC, and the device
will continue to operate from HFINTOSC until the external oscillator has
been restarted. Once the external source is operational, it is up to the
user to confirm that the clock source is stable and to switch the system
clock back to the external oscillator using the NOSC/NDIV bits.