PREINCx

PREINC

Indirect Data Register with pre-increment

This is a virtual register. The GPR/SFR register addressed by the FSRx register plus 1 is the target for all operations involving the PREINCx register. FSRx is incremented before the read or write operation.
  0x4EC,0x4E4,0x4DC 8   0,1,2 x
Parent topic: Register Definitions: Memory Organization

PREINC

Bit  7 6 5 4 3 2 1 0  
  PREINC[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:0 – PREINC[7:0]