I3CxERRIR1

I3CxERRIR1

Error Interrupt Flag 1

Notes:
  1. 1.Will not self-clear after the event. The user must clear this bit to re-arm.
  2. 2.In case of a race condition, user writes always take precedence over hardware events.
0x08B, 0x0BC 8     1index x

I3CxERRIR1

Bit  7 6 5 4 3 2 1 0  
          IBIAEIF MWLOEIF TXWEIF RXREIF  
Access          R/W/HS R/W/HS R/W/HS R/W/HS  
Reset          0 0 0 0  

Bit 3 – IBIAEIF: In-Band Interrupt Abort Error Interrupt Flag(1)

In-Band Interrupt Abort Error Interrupt Flag(1)

ValueDescription
1 In-Band Interrupt Abort from the Controller occurred
0 In-Band Interrupt Abort from the Controller not occurred

Bit 2 – MWLOEIF: Maximum Write Length Over Size Error Interrupt Flag(1)

Maximum Write Length Over Size Error Interrupt Flag(1)

ValueDescription
1 The Controller attempted to write one more byte than the Maximum Write Length size (I3CxMWL)
0 Write length violation not occurred

Bit 1 – TXWEIF: Transmit Buffer Write Error Interrupt Flag(1)

Transmit Buffer Write Error Interrupt Flag(1)

ValueDescription
1 Invalid write occurred; I3CxTXBwas written while TXBE=0
0 Invalid write not occurred

Bit 0 – RXREIF: Receive Buffer Read Error Interrupt Flag(1)

Receive Buffer Read Error Interrupt Flag(1)

ValueDescription
1 Invalid read occurred; I3CxRXB was read while RXBF=0
0 Invalid read not occurred