The filter, edge detector, and sequencer are, by default, clocked by the peripheral clock (CLK_PER). It is also possible to use other clock inputs (CLK_MUX_OUTn) to clock these blocks. This is configured by writing the Clock Source Selection (CLKSRC) bit field in the LUT Control A register.
When the Clock Source Selection (CLKSRC) bit is written to ‘1’,
LUTn-TRUTHSEL[2] is used to clock the corresponding filter and edge detector
(CLK_MUX_OUTn). The sequencer is clocked by the CLK_MUX_OUTn of the even LUT in the
pair. When CLKSRC is written to ‘1’, LUTn-TRUTHSEL[2] is treated as OFF
(low) in the truth table.
The CCL peripheral must be disabled while changing the clock source to avoid undefined outputs from the peripheral.