Whenever the debugger reads or writes a peripheral or memory location, the CRCSCAN will be disabled.
If the CRCSCAN is busy when the debugger accesses the device, the CRCSCAN will restart the ongoing operation when the debugger accesses an internal register or when the debugger disconnects.
The BUSY bit in the Status (CRCSCAN.STATUS) register will read
‘1
’ if the CRCSCAN was busy when the debugger caused it to disable, but
it will not actively check any section as long as the debugger keeps it disabled. There are
synchronized CRC status bits in the debugger's internal register space, which can be read
by the debugger without disabling the CRCSCAN. Reading the debugger's internal CRC status
bits will make sure that the CRCSCAN is enabled.
0
’ will stop the ongoing CRC operation (so that the
CRCSCAN does not restart its operation when the debugger allows it).1
’ will make the CRC start a single check with the
settings in the Control B (CRCSCAN.CTRLB) register, but not until the debugger
allows it.As long as the BUSY bit in CRCSCAN.STATUS is
‘1
’, CRCSCAN.CTRLB and the Non-Maskable Interrupt Enable (NMIEN)
bit in the Control A (CRCSCAN.CTRLA) register cannot be altered.
0
’ can trigger a Non-Maskable Interrupt (NMI) if the NMIEN
bit in CRCSCAN.CTRLA is ‘1
’. If an NMI has been triggered, no
writes to the CRCSCAN are allowed.1
’ will make the OK bit read as ‘1
’ when
the BUSY bit in CRCSCAN.STATUS is ‘0
’.Writes to CRCSCAN.CTRLA and CRCSCAN.CTRLB from the debugger are treated in the same way as writes from the CPU.