After a Power-on Reset (POR), the NVMCTRL rejects any write attempts to the NVM for a
certain time. During this period, the Flash Busy (FBUSY) and the EEPROM Busy (EEBUSY)
bit field in the NVMCTRL.STATUS register will read ‘1’. EEBUSY and
FBUSY bit field must read ‘0’ before the page buffer can be filled, or
NVM commands can be issued.
This time-out period is disabled either by writing the Time-Out Disable bit (TOUTDIS) in
the System Configuration 0 (FUSE.SYSCFG0) Fuse to ‘0’ or by configuring
the RSTPINCFG bit field in FUSE.SYSCFG0 Fuse to UPDI.